Identifying paths that fail or nearly fail timing requirements is a difficult problem all makers of high performance VLSI circuits face. Today's high performance microprocessors have millions of transistors and clock frequencies of up to 500 MHz. In the near future, we are likely to see microprocessors with 50 million transistors running at clock frequencies of 1 GHz and higher. This presents tremendous opportunity for signal paths to become timing hazards.
A diagnostics application that can identify timing failures is a key need for which there has heretofore been no known solution. A particularly frustrating problem occurs when an IC is exercised with functional patterns and performs successfully at longer cycle times, but fails as cycle times are shortened. The problem to be addressed by this invention is that of identifying what logical path(s) caused the failure in such circumstances; that is, which latch first contained an incorrect value, and along what logical path should the correct value have arrived. This problem is difficult to solve with current tools because when an incorrect value appears at an observable pinout, this gives little information on when an incorrect value was first latched in an internal memory element. There are no efficient ways to identify either the clock cycle at the end of which some memory element contains an incorrect value for the first time, or the fault containing memory element itself. There are several inefficient means for performing these tasks, such as using repeated scan outs, but they all require extensive manual intervention, as well as the ability to scan out (or observe by some other means) the contents of the "faulty" latch.